U.S. Pat. No. 8,652,962 discloses a method for forming a dual damascene metal interconnect for a semiconductor device. The method comprises providing a semiconductor substrate, forming gate structures on the substrate through front end of line processing, forming a dielectric layer over the gate structures, patterning vias through the dielectric layer, forming a sacrificial layer over the low-k dielectric layer, patterning trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer by means of a Chemical Mechanical Planarization (CMP) process, and forming an extremely low-k dielectric layer over the dielectric layer. This method aims at introducing low dielectric constant layers into semiconductor devices while avoiding damaging the extremely low-k dielectric. However, this method still introduces significant damage in the structures as it does not avoid defect formation in the metal structures, in the dielectric in which the vias are formed, and in the barrier lining the vias and trenches. There is, therefore, still a need for methods not suffering from these drawbacks.